The present invention relates to a semiconductor memory that must be periodically refreshed. More specifically, the present invention relates to a method and apparatus for performing refresh operations in a semiconductor memory during idle cycles of the memory.
Some conventional semiconductor memories, such as dynamic random access memory (DRAM), must be periodically refreshed in order to retain valid data. During refresh operations, external access typically is not allowed. In addition, a mechanism is required to inform the memory controller that the DRAM is performing a refresh operation. Any pending memory transaction has to be delayed until the refresh operation is completed. Refresh operations therefore lengthen the overall access time for memory accesses. It is therefore important to design a memory system in which the impact of refresh operations on external memory access is minimized.
Many different methods have been proposed to refresh these semiconductor memories. In one of these methods, which is commonly referred to as xe2x80x9cCAS before RAS,xe2x80x9d an external device signals a refresh operation by asserting a column access signal CAS# prior to asserting a row access signal RAS#. During normal accesses, the column address strobe signal RAS# is asserted before the column address strobe signal CAS#. In response to detecting the xe2x80x9cCAS before RASxe2x80x9d condition, the memory performs a refresh operation. The refresh operation typically is performed by reading the row of the memory to be refreshed. A xe2x80x9cCAS before RASxe2x80x9d refresh scheme is described in 1991 Memory Products Data Book, uPD424248 262,144xc3x974-Bit Dynamic CMOS RAM, NEC Electronics, pp 6-101 to 6-113. This reference also illustrates a hidden refresh that is a variation of the xe2x80x9cCAS before RASxe2x80x9d refresh method. These methods for refresh require handshake communication between the semiconductor memory and the external device, making the external device control the memory refresh.
Another conventional semiconductor memory that must be periodically refreshed is synchronous DRAM (SDRAM). One conventional SDRAM initiates refresh operations in response to control signals (i.e., RAS#, CAS#, CS#, WE# and CKE) received from an external device. These control signals are decoded to provide command codes that are used to control the refresh operations of the SDRAM. For example, when the control signals RAS#, CAS#, CS#, WE# and CKE have values of 0,0,0,1, and 1, a control code for initiating an auto refresh operation is generated. Similarly, when those same control signals have values of 0,0,0,1, and 0, a control code for initiating a self refresh operation is generated. This SDRAM is described in more detail IBM0316409C, 16 Mbit Synchronous DRAM data sheet, 1996, IBM Corporation.
Other synchronous DRAM have used explicit command codes for handling memory refresh. These include SLDRAM [4M=18 SLDRAM CONS400.P65xe2x80x94Rev. Sep. 22, 1997, 400 Mb/s/pin SLDRAM SLD4M18DR400 4M=18 SLDRAM Data Sheet, SLDRAM Consortium] and Rambus DRAM (RDRAM). [Direct Rambus Technology Disclosure, Oct. 15, 1997, Rambus Inc.] All of the above-described command codes are generated by the external device, and must be communicated to the memory device, thereby complicating the interface to the semiconductor memory. The interface then becomes incompatible with the interface of a simpler device, such as an SPAM.
Other conventional DRAM refresh schemes incorporate a dedicated refresh control signal. These schemes are exemplified by enhanced DRAM (EDRAM) [DM2202/2212 EDRAM, 1 Mbxc3x974 Enhanced Dynamic RAM, 1994, Ramtron International Corporation] and cache DRAM (CDRAM) [Dosaka et. al, U.S. Pat. No. 5,559,750]. In both the EDRAM and the CDRAM, a dedicated external refresh signal is used to initiate refresh operations. As noted with the external signals of the aforementioned devices, this additional external signal is incompatible with an SRAM and other simple interface devices.
Schemes for performing refresh operations during unused idle memory cycles of a DRAM are described in U.S. Pat. No. 6,078,547 entitled xe2x80x9cMethod And Structure For Controlling Operation Of A DRAM Arrayxe2x80x9d, U.S. Pat. No. 6,028,804 entitled xe2x80x9cMethod And Apparatus For 1-T SRAM Compatible Memoryxe2x80x9d, U.S. Pat. No. 5,999,474 entitled xe2x80x9cMethod And Apparatus For Complete Hiding Of The Refresh Of A Semiconductor Memoryxe2x80x9d, and U.S. Pat. No. 6,075,740 entitled xe2x80x9cMethod And Apparatus For Increasing The Time Available For Refresh For 1-T SRAM Compatible Devicesxe2x80x9d, all by the present inventor.
Accordingly, the present invention provides a memory system having a memory controller and one or more memory blocks that are commonly coupled to a system bus. Each memory block includes an array of memory cells that must be periodically refreshed to retain valid data. Each memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array.
The memory controller includes a refresh manager that monitors the number of idle cycles on the system bus during a refresh period, and forces one or more idle cycles on the system bus if the monitored number of idle cycles is less than a predetermined number of idle cycles during the refresh period. For example, in one embodiment, the refresh period for eight rows of memory cells is 20.48 microseconds. If the refresh manager detects fewer than eight idle cycles on the system bus during the 20.48 microsecond refresh period, then the refresh manager forces the appropriate number of idle cycles onto the system bus at the end of the refresh period. For example, if the refresh manager only detects six idle cycles on the system bus during the refresh period, then the refresh manager will force two additional idle cycles on the system bus at the end of the refresh period. As a result, eight idle cycles are provided on the system bus. Each of the memory blocks performs a pending refresh operation during an idle cycle on the system bus. As a result, the eight rows of memory cells are always refreshed within eight cycles of the end of the refresh period (or shorter). There is a relatively high probability that the refresh manager will not have to force any idle cycles at the end of the refresh period. Moreover, even if idle cycles must be forced, the maximum time required for these idle cycles represents a small fraction of the refresh period (e.g., 0.4 percent).
While idle cycles are being forced, the refresh manager asserts a control signal that informs accessing clients of the memory system that memory accesses must be deferred. After the idle cycles have been forced, the refresh manager de-asserts the control signal to inform the accessing clients that memory accesses can proceed.
In a particular embodiment, the refresh manager includes an idle cycle counter for counting the number of idle cycles on the system bus. When the number of idle cycles on the system bus is equal to the predetermined number of idle cycles, the idle cycle counter generates a FULL signal. A refresh counter is coupled to receive the FULL signal. If the refresh counter determines that the refresh period expires prior to receiving the FULL signal from the idle cycle counter, then the refresh counter asserts a control signal that forces idle cycles on the system bus. If the refresh counter receives the FULL signal prior to the expiration of the refresh period, the refresh counter is reset, thereby beginning a new refresh period.
Within each memory block, an access arbiter receives external access requests (which are initiated by the memory controller) and refresh requests (which are generated within the memory block). The access arbiter always grants priority to any pending external access request. The access arbiter will allow refresh requests to be granted only if there are no pending external access requests. As a result, the refresh requests do not impede the external access requests. The refresh operations are performed during naturally occurring idle cycles or during the forced idle cycles.
In another embodiment, the memory blocks are logically divided into two or more sets. In this embodiment, the refresh manager monitors the number of idle cycles occurring in each set of memory blocks during the refresh period. The refresh manager forces idle cycles on the system bus only if the number of idle cycles occurring in at least one set of memory blocks during the refresh period is less than the predetermined number of idle cycles.
In yet another embodiment of the present invention, the refresh manager is modified to force a predetermined number of idle cycles on the system bus after the refresh period has expired, regardless of the number of idle cycles occurring during the refresh period. For example, the refresh manager can force eight idle cycles at the end of each refresh period.
Another embodiment of the present invention includes the steps of (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks upon receiving the asserted timing signal; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted.
A memory system for implementing this method includes a memory controller, one or more memory blocks and a system bus. The memory controller and each of the memory blocks are coupled to the system bus. Each memory block includes an array of memory cells that must be periodically refreshed, a refresh timer, a refresh detector, an access arbiter, and a logic circuit.
The refresh timer in each block periodically asserts a refresh timing signal. For example, the refresh timer may periodically assert a refresh timing signal every 256 clock cycles. The refresh detector in each block is coupled to receive the refresh timing signal. If the refresh timing signal is asserted, refresh detector will assert a refresh pending signal.
The access arbiter in each block is coupled to receive the refresh pending signal. If the refresh pending signal is asserted, and an idle cycle exists in the memory block, then access arbitrator will enable a refresh operation to be performed in the memory block. Upon enabling a refresh operation, the access arbiter asserts a refresh acknowledge signal.
Within each block, the refresh acknowledge signal is provided to the refresh detector. Each refresh detector receiving an asserted refresh acknowledge signal de-asserts the corresponding refresh pending signal.
Within each block, the logic circuit is coupled to receive the corresponding refresh pending and refresh timing signals. Each logic circuit that receives both an asserted refresh pending signal and an asserted refresh timing signal pulls down on a dedicated refresh line of the system bus. That is, each logic circuit that has not performed a refresh operation by the time the refresh timing signal is asserted pulls down on the refresh line. The signal on the refresh line is referred to as the refresh forcing signal.
The memory controller is coupled to receive the refresh forcing signal on the refresh line of the system bus. If the refresh forcing signal is pulled down to a logic low value, the memory controller forces an idle cycle on the system bus. This enables all of the memory blocks to be properly refreshed.
Another embodiment of the present invention includes a method of operating a memory system having a plurality of memory blocks. This method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks upon receiving the asserted timing signal; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted.
A memory system for implementing this method includes a memory controller, one or more memory blocks and a system bus. The memory controller and each of the memory blocks is coupled to the system bus. Each memory block includes an array of memory cells that must be periodically refreshed, a refresh timer, a refresh detector, an access arbiter, and a logic circuit.
In an alternate embodiment, a common refresh timer can be shared among the memory blocks. This arrangement is particularly suitable in an integrated environment where the entire memory system resides on the same silicon substrate. Furthermore the timing signal generated by the refresh timer can be arranged to propagate through a daisy-chain connecting serially to all the memory blocks. Such a scheme is described in detail in pending U.S. patent application Ser. No. 09/405,607 xe2x80x9cRead/Write Buffers For Complete Hiding Of The Refresh of A Semiconductor Memory And Method Of Operating Samexe2x80x9d by Wingyu Leung.
The refresh timer in each block periodically asserts a refresh timing signal. For example, the refresh timer may periodically assert a refresh timing signal every 256 clock cycles. The refresh detector in each block is coupled to receive the refresh timing signal. If the refresh timing signal is asserted, refresh detector will assert a refresh pending signal.
The access arbiter in each block is coupled to receive the refresh pending signal. If the refresh pending signal is asserted, and an idle cycle exists in the memory block, then access arbitrator will enable a refresh operation to be performed in the memory block. Upon enabling a refresh operation, the access arbiter asserts a refresh acknowledge signal.
Within each block, the refresh acknowledge signal is provided to the refresh detector. Each refresh detector receiving an asserted refresh acknowledge signal de-asserts the corresponding refresh pending signal.
Within each block, a logic circuit is coupled to receive the corresponding refresh pending signal. Each logic circuit that receives an asserted refresh pending signal pulls down on a dedicated refresh line of the system bus. That is, each logic circuit pulls down on the refresh line until a refresh operation is performed by the memory block. The signal on the refresh line is referred to as the refresh forcing signal.
The memory controller is coupled to receive the refresh forcing signal on the refresh line of the system bus. If the memory controller detects that the refresh line is continuously pulled down to a logic low level for a predetermined time period, then the memory controller forces an idle cycle on the system bus. This enables all of the memory blocks to be properly refreshed.
The present invention will be more fully understood in view of the following description and drawings.